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RF3196
QUAD-BAND GSM850/GSM900/DCS/PCS POWER AMP MODULE
RoHS Compliant and Pb-Free Product Package Style: Module, 6mm x6mm
Features
Reduced Current into Mismatch Ultra-Small 6mmx6mm Package Size Integrated VREG Complete Power Control Solution Automatic VBATT Tracking Circuit No External Components or Routing
DCS/PCS 1 RFIN BAND SELECT 2 TX ENABLE 3 VBATT 4 GND 5 VRAMP 6 GSM 7 RF IN 8 GSM RFOUT 9 DCS/PCS RFOUT
Applications
3V Quad-Band GSM Handsets Commercial and Consumer Systems Portable Battery-Powered Equipment GSM850/EGSM900/DCS/PC S Products GPRS Class 8 Power StarTM Module
Functional Block Diagram
Product Description
The RF3196 is a high-power, high-efficiency power amplifier module with integrated power control that provides over 50dB of control range. The device is a self-contained 6mmx6mm module with 50 input and output terminals. The device is designed for use as the final RF amplifier in GSM850, EGSM900, DCS and PCS handheld digital cellular equipment and other applications in the 824MHz to 849MHz, 880MHz to 915MHz, 1710MHz to 1785MHz and 1850MHz to 1910MHz bands. The RF3196 incorporates RFMD's latest VBATT tracking circuit, which monitors battery voltage and prevents the power control loop from reaching saturation. The RF3196 also has a power flattening circuit that reduces power variation and max current draw into mismatch. The RF3196 requires no external routing or external components, simplifying layout and reducing board space.
Ordering Information
RF3196 RF3196 SB RF3196PCBA-41X Quad-Band GSM850/GSM900/DCS/PCS Power Amp Module Power Amp Module 5-Piece Sample Pack Fully Assembled Evaluation Board
Optimum Technology Matching(R) Applied
GaAs HBT GaAs MESFET InGaP HBT SiGe BiCMOS Si BiCMOS SiGe HBT GaAs pHEMT Si CMOS Si BJT GaN HEMT
RF MICRO DEVICES(R), RFMD(R), Optimum Technology Matching(R), Enabling Wireless ConnectivityTM, PowerStar(R), POLARISTM TOTAL RADIOTM and UltimateBlueTM are trademarks of RFMD, LLC. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. (c)2006, RF Micro Devices, Inc.
Rev A2 DS071207
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Absolute Maximum Ratings Parameter
Supply Voltage Power Control Voltage (VRAMP) Input RF Power Max Duty Cycle Output Load VSWR Operating Case Temperature Storage Temperature
Rating
-0.3 to +6.0 -0.3 to +2.2 +10 50 10:1 -20 to +85 -55 to +150
Unit
VDC V dBm % C C
Caution! ESD sensitive device.
Exceeding any one or a combination of the Absolute Maximum Rating conditions may cause permanent damage to the device. Extended application of Absolute Maximum Rating conditions to the device may reduce device reliability. Specified typical performance or functional operation of the device under Absolute Maximum Rating conditions is not implied. RoHS status based on EUDirective2002/95/EC (at time of this document revision). The information in this publication is believed to be accurate and reliable. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents, or other rights of third parties, resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RFMD. RFMD reserves the right to change component circuitry, recommended application circuitry and specifications at any time without prior notice.
Operating Conditions Parameter
Overall Power Control VRAMP
Power Control "ON" Power Control "OFF" VRAMP Input Capacitance VRAMP Input Current TX Enable "ON" TX Enable "OFF" GSM Band Enable DCS/PCS Band Enable 1.5 3.0 3.5 1 150 4.5 1.5 0.5 0.5 0.26 2 20 30 2.1 V V pF A V V V V V A mA V V A V V A Operating limits PIN <-30dBm, TX Enable=Low, Temp=-20C to +85C VRAMP =0.26V, TX Enable=High Max. POUT Min. POUT DC to 2MHz VRAMP =2.1V
Min.
Specification Typ.
Max.
Unit
Condition
Overall Power Supply
Power Supply Voltage Power Supply Current
Overall Control Signals
Band Select "Low" Band Select "High" Band Select "High" Current TX Enable "Low" TX Enable "High" TX Enable "High" Current 0 1.5 0 1.5 0 2.0 20 0 2.0 1 0.5 3.0 50 0.5 3.0 2
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RF3196
Parameter Min. Specification Typ. Max. Unit Condition
Nominal conditions: Temp=+25 C, VBATT =3.5V, VRAMP =VRAMP_RP, PIN =3dBm, Freq=824MHz to 849MHz, 12.5% Duty Cycle, Pulse Width=1154s 824 to 849 34.2 32.0 45 0 51 +3 -85 -45 -30 -30 -15 -30 -30 -10 -20 -10 -15 -36 50 2.5:1 -36 dBm VSWR=8:1; all phase angles (VRAMP set for POUT <34.2dBm into 50 load; load switched to VSWR=8:1; RBW=3MHz) VSWR=10:1; all phase angles (VRAMP set for POUT <34.2dBm into 50 load; load switched to VSWR=10:1) dB -23 dBm Load impedance presented at RF OUT pad VRAMP =0.26V to VRAMP_RP VRAMP =VRAMP_RP +5 MHz dBm dBm % dBm dBm dBm dBm dBm dBm dBm dBm Temp=+25C, VBATT =3.5V, VRAMP =VRAMP_RP Temp=+85C, VBATT =3.0V, VRAMP <2.1V At POUT MAX, VBATT =3.5V, VRAMP =2.1V Maximum output power guaranteed at minimum drive level RBW=100kHz, 869MHz to 894MHz, POUT < +34.2dBm TXEnable=Low, PIN =+5dBm TXEnable=High, PIN =+5dBm, VRAMP =0.26V VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to VRAMP_RP
Overall (GSM850 Mode)
Operating Frequency Range Maximum Output Power 1 Maximum Output Power 2 Total Efficiency Input Power Range Output Noise Power Forward Isolation 1 Forward Isolation 2 Cross Band Isolation at 2f0 Second Harmonic Third Harmonic All Other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Stability (Spurious Emissions) Output Load VSWR Ruggedness No damage or permanent degradation to device 50 50 55 -35
Output Load Impedance
Power Control VRAMP
Power Control Range Transient Spectrum Notes: VRAMP_RP =VRAMP set for 34.2dBm at nominal conditions.
Rev A2 DS071207
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Parameter Min. Specification Typ. Max. Unit Condition
Nominal conditions: Temp=+25 C, VBATT =3.5V, VRAMP =VRAMP_RP, PIN =3dBm, Freq=880MHz to 915MHz, 12.5% Duty Cycle, Pulse Width=1154s 880 to 915 34.2 32.0 50 0 56 +3 -83 -85 Forward Isolation 1 Forward Isolation 2 Cross Band Isolation 2f0 Second Harmonic Third Harmonic All Other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Stability (Spurious Emissions) Output Load VSWR Ruggedness No damage or permanent degradation to device 50 50 55 -35 -23 dB dBm 50 2.5:1 -36 dBm VSWR=8:1; all phase angles (VRAMP set for POUT <34.2dBm into 50 load; load switched to VSWR=8:1; RBW=3MHz) VSWR=10:1; all phase angles (VRAMP set for POUT <34.2dBm into 50 load; load switched to VSWR=10:1) Load impedance presented at RF OUT pad VRAMP =0.26V to VRAMP_RP VRAMP =VRAMP_RP -40 -30 -30 -15 -30 -30 -10 -20 -10 -15 -36 +5 MHz dBm dBm % dBm dBm dBm dBm dBm dBm dBm dBm dBm Temp=+25C, VBATT =3.5V, VRAMP =VRAMP_RP Temp=+85C, VBATT =3.0V, VRAMP <2.1V At POUT MAX, VBATT =3.5V, VRAMP =2.1V Maximum output power guaranteed at minimum drive level RBW=100kHz, 925MHz to 935MHz, POUT < +34.2dBm RBW=100kHz, 935MHz to 960MHz, POUT < +34.2dBm TXEnable=Low, PIN =+5dBm TXEnable=High, PIN =+5dBm, VRAMP =0.26V VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to VRAMP_RP
Overall (GSM900 Mode)
Operating Frequency Range Maximum Output Power 1 Maximum Output Power 2 Total Efficiency Input Power Range Output Noise Power
Output Load Impedance
Power Control VRAMP
Power Control Range Transient Spectrum Notes: VRAMP_RP =VRAMP set for 34.2dBm at nominal conditions.
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Parameter
Overall (DCS Mode)
Operating Frequency Range Maximum Output Power 1 Maximum Output Power 2 Total Efficiency Input Power Range Output Noise Power Forward Isolation 1 Forward Isolation 2 Second Harmonic Third Harmonic All Other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Stability (Spurious Emissions) Output Load VSWR Ruggedness No damage or permanent degradation to device 50 45 50 -35 -23 dB dBm 50 2.5:1 -36 dBm VSWR=8:1; all phase angles (VRAMP set for POUT <32dBm into 50 load; load switched to VSWR=8:1; RBW=3MHz) VSWR=10:1; all phase angles (VRAMP set for POUT <32dBm into 50 load; load switched to VSWR=10:1) Load impedance presented at RF OUT pad VRAMP =0.26V to VRAMP_RP VRAMP =VRAMP_RP 32.0 30.0 45 0 51 +3 -85 -40 -25 -15 -30 -30 -10 -10 -15 -36 +5 1710 to 1785 MHz dBm dBm % dBm dBm dBm dBm dBm dBm dBm Temp=+25C, VBATT =3.5V, VRAMP =VRAMP_RP Temp=+85C, VBATT =3.0V, VRAMP < 2.1V At POUT MAX, VBATT =3.5V, VRAMP =2.1V Maximum output power guaranteed at minimum drive level RBW=100kHz, 1805MHz to 1880MHz, POUT < 32dBm TXEnable=Low, PIN =+5dBm TXEnable=High, VRAMP =0.26V, PIN =+5dBm VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to VRAMP_RP
Min.
Specification Typ.
Max.
Unit
Condition
Nominal conditions: Temp=25C, VBATT =3.5V, VRAMP =VRAMP_RP, PIN =3dBm, Freq=1710MHz to 1785MHz, 12.5% Duty Cycle, pulse width=1154s
Output Load Impedance
Power Control VRAMP
Power Control Range Transient Spectrum Notes: VRAMP_RP =VRAMP set for 32dBm at nominal conditions.
Rev A2 DS071207
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Parameter
Overall (PCS Mode)
Operating Frequency Range Maximum Output Power 1 Maximum Output Power 2 Total Efficiency Input Power Range Output Noise Power Forward Isolation 1 Forward Isolation 2 Second Harmonic Third Harmonic All Other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Stability (Spurious Emissions) Output Load VSWR Ruggedness No damage or permanent degradation to device 50 45 50 -35 -23 dB dBm 50 2.5:1 -36 dBm VSWR=8:1; all phase angles (VRAMP set for POUT <32dBm into 50 load; load switched to VSWR=8:1; RBW=3MHz) VSWR=10:1; all phase angles (VRAMP set for POUT <32dBm into 50 load; load switched to VSWR=10:1) Load impedance presented at RF OUT pad VRAMP =0.26V to VRAMP_RP VRAMP =VRAMP_RP 32.0 30.0 45 0 51 +3 -85 -35 -25 -15 -30 -30 -10 -10 -15 -36 +5 1850 to 1910 MHz dBm dBm % dBm dBm dBm dBm dBm dBm dBm Temp=+25C, VBATT =3.5V, VRAMP =VRAMP_RP Temp=+85C, VBATT =3.0V, VRAMP < 2.1V At POUT MAX, VBATT =3.5V, VRAMP =2.1V Maximum output power guaranteed at minimum drive level RBW=100kHz, 1930MHz to 1990MHz, POUT < 32dBm TXEnable=Low, PIN =+5dBm TXEnable=High, VRAMP =0.26V, PIN =+5dBm VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to VRAMP_RP
Min.
Specification Typ.
Max.
Unit
Condition
Nominal conditions: Temp=25C, VBATT =3.5V, VRAMP =VRAMP_RP, PIN =3dBm, Freq=1850MHz to 1910MHz, 12.5% Duty Cycle, pulse width=1154s
Output Load Impedance
Power Control VRAMP
Power Control Range Transient Spectrum Notes: VRAMP_RP =VRAMP set for 32dBm at nominal conditions.
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RF3196
Pin 1 2 Function Description DCS/PCS IN RF input to the DCS band. This is a 50 input.
BAND SELECT
Allows external control to select the GSM or DCS band with a logic high or low. A logic low enables the GSM band whereas a logic high enables the DCS band.
Interface Schematic
BAND SEL TX EN
GSMCTRL
DCS CTRL
3
TX ENABLE
This signal enables the PA module for operation with a logic high.
VBATT
TX EN
TX ON
4 5 6 7 8 9 Pkg Base
VBATT GND VRAMP GSM IN GSM OUT DCS/PCS OUT GND
Power supply for the module. This should be connected to the battery. Ramping signal from DAC. A 300kHz lowpass filter is integrated into the CMOS. No external filtering is required.
VRAMP
300 kH z
RF input to the GSM band. This is a 50 input. RF output for the GSM band. This is a 50 output. The output load line matching is contained internal to the package. RF output for the DCS band. This is a 50 output. The output load line matching is contained internal to the package.
Package Drawing
1
1.20 0.04
6.00 0.10
6.00 0.10 Shaded areas represent pin 1.
Dimensions in mm.
0.100 TYP 0.565 TYP 0.965 1.150 TYP 1.225 TYP 1.750 TYP
2.600 TYP 4.650
5.823 5.500 5.400 TYP 5.225 TYP 5.200 TYP 4.625 TYP 4.450 TYP 3.850 TYP 3.675 TYP 3.075 TYP 2.900 TYP 2.300 TYP 2.125 TYP 1.525 TYP 1.350 TYP 0.800 TYP 0.600 TYP 0.500 TYP 0.000
1
0.000 TYP 0.565 TYP 1.150 TYP 2.000 TYP 2.850 5.057 5.100
Rev A2 DS071207
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5.435 TYP 5.500 TYP 5.900 TYP
5.900 TYP 5.435 5.370 5.035 4.600 4.300 4.200 3.800 3.400 3.065 3.000 2.600 2.100 1.700 1.365 1.300 0.900 TYP 0.750 TYP 0.565 TYP 0.100 TYP
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Pin Out
Top Down View
DCS/PCS 1 RFIN BAND SELECT 2 TX ENABLE 3 VBATT 4 GND 5 VRAMP 6 GSM 7 RF IN 8 GSM RFOUT 9 DCS/PCS RFOUT
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Rev A2 DS071207
RF3196
Application Schematic
50 strip DCS/PCS IN BAND SELECT TX ENABLE VBATT 1 2 3 4 5 VRAMP GSM IN 50 strip 6 7 8 50 strip GSM OUT 9 50 strip DCS/PCS OUT
Evaluation Board Schematic
P1 1 GND P2-1 CON1 50 strip DCS/PCS IN 1 BAND SELECT TX ENABLE
*Not required in most applications.
P2 1 VCC CON1
50 strip 9 DCS/PCS OUT 2 3
VBATT
4 5 6 50 strip 8 GSM OUT
22 F* VRAMP 50 strip GSM IN
7
Notes: 1. All the PA output measurements are referenced to the PA output pad (pins 8 and 9). 2. The 50 strip between the PA output pad and the SMA connector has an approximate insertion loss of 0.1 dB for GSM900/EGSM900 and 0.2 dB for DCS1800/PCS1900 bands.
Rev A2 DS071207
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Evaluation Board Layout
Board Size 2.0" x 2.0" Board Thickness 0.032", Board Material FR-4, Multi-Layer
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Rev A2 DS071207
RF3196
Theory of Operation
Overview Building on previous generations of PowerStar(R) modules, the RF3196 has integrated Power Control with additional features such as VBATT tracking, and a power flattening circuit that reduces power and current variation into mismatch conditions. Theory of Operation The type of power control used in the RF3196 is a closed loop method that regulates the collector voltage of the amplifier while the stages are held at a constant bias. As the required output power is decreased from full power down to minimum PCLs, the collector voltage is also decreased. This process is repeatable and enables the user to implement a single point calibration, thereby increasing production by saving valuable time in the factory. The basic circuit is shown below in Figure 1.
VBATT
VRAMP 3 dB BW 300 kHz + + H(s) VCC Saturation Detector
RF IN TX ENABLE
RF OUT
Figure 1. Power Control Circuit Output power does not vary due to supply voltage under normal operating conditions if VCC is sufficiently lower than VBATT. Regulating the collector voltage to the PA essentially eliminates voltage sensitivity. This covers most cases where the PA will be operated. However, as the battery discharges and approaches its lower voltage range, the maximum output power from the PA will also drop slightly. In this case it is important to decrease VRAMP to prevent the power control circuitry from inducing switching transients. These transients occur as a result of the control loop slowing down and not regulating power in accordance with VRAMP.. In the RF3196, is a VBATT tracking circuit that reduces the level of VRAMP as the battery voltage decreases. The limiter is integrated into the CMOS controller and requires no additional input from the user. In the circuit, a feedback loop is implemented that compares VBATT to VCC and produces a correction so that VRAMP is decreased. This prevents the switch transistor from being driven into saturation and inducing switching transients. In addition to the VBATT tracking circuit, the RF3196 has an integrated power flattening circuit that reduces the amount of current variation when a mismatch is presented to the output of the PA. When a mismatch is presented to the output of the PA, its output impedance is varied and could present a load that will increase output power. As the output power increases, so does current consumption. The current consumption can become very high if not monitored and limited. The power flattening circuit, like the VBATT tracking circuit, is also integrated onto the CMOS controller and requires no input from the user.
Rev A2 DS071207
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Into a mismatch, the current varies as the phase changes. The power flattening circuit monitors current through an internal sense resistor. As the current changes, the loop is adjusted in order to maintain current. The result is flatter power and reduced current into mismatch. When compared to the RF3166, the RF3196 shows less current variation and has less power variation. Below, in Figure 2, is the power variation comparison.
Power Variation VSWR=3:1
35.8 35.6 35.4 35.2 35.0 34.8 34.6 34.4 34.2 34.0 33.8 33.6 33.4 33.2 33.0 32.8 32.6 32.4 32.2 0 20 40 60 80 10 12 14 16 18 20 22 24 26 28 30 32 34 36 00000000000000
VRAMP=VRAMPRP=34.2dBm into 50 Freq=880, Temp=Room, PIN=5dBm, VBATT=4.5V
RF3196 RF3166
POUT (dBm)
Phase Angle ()
Figure 2. Power Variation into Mismatch As previously discussed, reducing the power variation results in reduced current variation. Below, in Figure 3, is the current variation comparison.
Current Variation VSWR=3:1
3.0 2.8 2.6 2.4 2.2 2.0 1.8
VRAMP=VRAMPRP=34.2dBm into 50 Freq=880, Temp=Room, PIN=5dBm, VBATT=4.5V
RF3196 RF3166
ICC (A)
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 20 40 60 80 10 12 14 16 18 20 22 24 26 28 30 32 34 36 00000000000000
Phase Angle ()
Figure 3. Current Variation into Mismatch
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Rev A2 DS071207
RF3196
The power control functionality provides 50dB continuous control range and 70dB total control range, using a DAC compatible analog voltage input referred to as VRAMP. The timing of the control signals is important for maintaining transient performance and superior isolation between the bursts. To ensure that the part ramps up properly, a timing diagram is provided below in Figure 4. It is important that ramping begins at least 2us after TXEN goes high. An offset voltage of 0.26V provides the greatest dynamic range for the best transient performance.
VBATT
2.9 V to 4.2 V
2.5V
BandSel
0 to 5 dBm
RF Drive
> 1.8V
TX_Enable Vramp starts 2us after Tx_Enable
0.26 to 2.1 V
Vramp ends 2us before Tx_Enable
VRAMP
Power On Sequence:
Apply VBATT Apply Band Select Apply RF drive Apply TX_Enable & VRAMP in unison
The Power Down sequence is in opposite order of the Power On Sequence
Figure 4. RF3196 Timing Diagram As described in the above figure, VBATT is applied first to provide bias to the silicon control chip. Then the RF drive is applied. Finally, when TX_ENABLE is high, the VRAMP signal is held at constant 0.26V, and 2uS later, VRAMP begins to ramp up. The shape of VRAMP is important for maintaining the switching transients. The basic shape of the ramping function should be the first 90 of a raised sine function. This is shown in Equation 1 where A is the desired peak power in mW, B is the minimum output power of the power amplifier in mW, K determines the duration of the ramp, and t is time. The down-ramp function uses the same equation except a cosine function is used in the place of the sine function. The exponent "n" determines the steepness of the ramp and is typically set to 5.
P OUT ( mW ) = ( A - B ) ( sin ( Kt ) ) + B
The value of K is calculated using Equation 2.
n
(Eq. 1)
K = ------------------2 t ramp
(Eq. 2)
The Ramp synthesis tool provided by RFMD generates the ramp profiles automatically. It will generate ramps for all power levels and output the waveform for 8, 10, and 12 bit DACs in decimal, voltage, or hex formats.
Rev A2 DS071207
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The spectrum is maintained at all power levels. The following figures show power ramping at max and backed off power.
Figure 5. Full Power Ramping
Figure 6. Low Power Ramping Summary The RF3196 is the next generation of PowerStar(R) Power Amplifiers. The type of power control used in the RF3196 is a closed loop method that regulates the collector voltage of the amplifier while the stages are held at a constant bias. The VBATT tracking circuit monitors VBATT levels so that the transient spectrum never degrades and the new power flattening circuit reduces power and current variation in high current situations.
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Rev A2 DS071207
RF3196
PCB Design Requirements
PCB Surface Finish The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land Pattern
A = 0.40 Sq. Typ. B = 0.80 x 0.40 Typ. C = 0.40 x 0.80
0.37 0.93 4.47 5.20 5.60
Dimensions in mm.
A = 0.55 x 0.95 B = 0.55 Sq. Typ. C = 0.95 x 0.55 Typ. D = 1.80 x 4.62 E = 0.60 Sq. Typ.
5.20 TYP 4.10 3.30 2.50 1.60
Pin 1
Pin 1
5.20 4.10 3.30 2.50 1.80 1.40 0.80 0.00
C A A B
B
5.60 5.40 4.90
A B B C B B B D
E E E E E E E E E E E E E E E
C B B B B B B B
5.40 4.62 3.85 3.07 2.76 2.30 1.52 0.75
A A A
0.60 0.20
0.80 0.00
0.00 0.50
4.90 5.40
0.00
1.95
3.40
4.25
Metal Land Pattern
Solder Mask Pattern
Figure 1. PCB Metal Land and Solder Mask Patterns (Top View) PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier. Thermal Pad and Via Design Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results.
Rev A2 DS071207
7628 Thorndike Road, Greensboro, NC 27409-9421 * For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
5.40
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Material Declaration
RoHS* Banned Material Content
RoHS Compliant: Compliance Date Code: Bill of Materials Revision: Pb Free Category: Yes N/A 3196E4.9 Rev.B e4 Parts Per Million (PPM) Pb 1000 0 335 0 0 0 0 0 Cd 0 0 0 0 0 0 0 0 Hg 0 0 0 0 0 0 0 0 Cr VI 0 0 0 0 0 0 0 0 PBB 0 0 0 0 0 0 0 0 PBDE 0 0 0 0 0 0 0 0 Package total weight in grams (g): 0.117
Bill of Materials Permissible Concentration Limits per EU Decision 2005/618/EC Substrate Passive Components Die Molding Compound Die Attach Epoxy Wire Solder Plating
This RoHS banned material content declaration was prepared solely on information, including analytical data, provided to RFMD by its suppliers, and applies to the Bill of Materials (BOM) revision noted above. * DIRECTIVE 2002/95/EC OF THE EUROPEAN PARLIAMENT AND OF THE COUNCIL of 27 January 2003 on the restriction of the use of certain hazardous substances in electrical and electronic equipment. Pb noted in this material declaration is used in glass or ceramics in electronic components which is an allowed exemption from the RoHS regulations, see Annex to Directive 2002/95/EC and amendment 2005/747/EC.
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Rev A2 DS071207

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